1. Field of the Invention
Embodiments of the invention relate to a method for forming fine patterns of a semiconductor device. In particular, embodiments of the invention relate to a method for forming fine patterns of a semiconductor device using hard mask patterns characterized by a relatively fine pitch and formed through double patterning.
This application claims priority to Korean Patent Application No. 10-2006-0101028, filed on Oct. 17, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In order to fabricate semiconductor devices having high degrees of integration, very small patterns must be formed. Additionally, individual elements may be made smaller in order to increase the number of elements disposed in a selected area of a semiconductor device. Making individual elements smaller may be accomplished by reducing the pitch that characterizes a plurality of patterns formed in a semiconductor device. “Pitch” is defined as the sum of the width of a pattern and the distance between the pattern and an adjacent pattern. Presently, due to resolution restrictions of photolithography techniques, the drastic decrease in the design rule for semiconductor devices has reached a limit with regard to how small of a pitch characterizing a plurality of patterns may be. In particular, because of the resolution restrictions of photolithography techniques for forming a device isolation region that defines an active region in a substrate, and for forming a line and space (L/S) pattern, the ability to form patterns characterized by a pitch that is as small as desired is limited.
In order to overcome the limitations mentioned above, methods for forming hard mask patterns characterized by a fine pitch (i.e., a relatively small pitch) using double patterning have been suggested. In one of the suggested methods, polysilicon is used as an etch mask material for forming the hard mask patterns. However, when using polysilicon as an etch mask material for forming hard mask patterns, desired etching characteristics cannot be obtained because, when the polysilicon etch mask remains as a hard mask pattern, the polysilicon is exposed to harsh environmental conditions that characterize conventional etching processes. For example, when a tungsten (W) film is formed under a hard mask and the tungsten (W) film is etched using the hard mask pattern as an etch mask, some fluoride (F) atoms of the etchant used for etching the tungsten (W) film are lost due to a chemical reaction between fluoride (F) atoms of the etchant and silicon (Si) atoms of the polysilicon. Thus, not all of the etchant used for etching the tungsten (W) film actually etches the tungsten (W) film. Consequently, the rate at which the tungsten (W) film is etched is reduced, and a sidewall profile of a tungsten (W) film pattern formed through the etching process has an inclined shape with a relatively large angle of inclination.
Also, when the height of the polysilicon film remaining on the hard mask pattern is not uniform, a sidewall profile of a trench formed in a semiconductor substrate will be formed asymmetrically because etchant will be scattered in an edge portion of the polysilicon film when etching a substrate using the hard mask pattern as an etch mask to form a device isolation trench. Thus, operational characteristics of the semiconductor devices may be adversely affected and product yield may be reduced.